Enhancing the Performance of Industrial Controllers by Using Field Programmable Gate Array Based Modules

Enhancing the Performance of Industrial Controllers by Using Field Programmable Gate Array Based Modules

Macia, N F

Abstract

Industrial controllers such as Programmable Logic Controllers (PLC) are industrial devices that are frequently used in process automation. Internally, they use microprocessors to execute programs written using different programming language techniques such as Ladder Logic Diagrams, Function Block Diagrams and others. Since the microprocessor executes instructions sequentially, the time to execute the programs increases as the number of computationally intensive control algorithms is increased. Industrial controllers are increasingly being used in networked environments to reduce cost and for better asset management. The networking protocols used for networking in these environments often change to introduce new features and enhance existing features. These changes are primarily accomplished by adding communication modules to the PLC. The problems of increased execution time and increase in the cost of the overall control system caused by the addition of the new modules can be reduced by using programmable logic devices such as Field Programmable Gate Arrays (FPGA). Since FPGAs are highly configurable, multiple communication/control modules can be implemented on a single device. The cost of FPGA-based systems is usually low because of the lower non-recurring engineering costs. This paper presents details of a project in which a Xilinx FPGA was used to implement a control algorithm and a serial communication protocol. The paper brings out the advantages of using a FPGA in conjunction with an industrial controller.

(ProQuest-CSA LLC: … denotes formulae omitted.)

I. Introduction

Industrial controllers such as Programmable Logic Controllers are widely used in industrial automation and process control. A Programmable Logic Controller uses a general-purpose microprocessor to execute the program and connect to the external devices using different input and output modules. Since microprocessors execute instructions sequentially, the response time of the controller increases as the number and complexity of the control algorithms increases. These industrial controllers are increasingly being used in networked environments to work with other control/monitoring systems. The manufacturers of many of these industrial controllers provide dedicated modules to support different networking protocols. These protocols are occasionally changed sometimes to increase the performance or to add new functionality. The modification of these protocols often involves changing the existing modules. Sometimes multiple networking modules are needed to integrate different systems. The addition of these modules increases the cost of the system. The problems of increased execution time and increase in the cost of the system because of the additional new modules can be reduced by using programmable logic devices such as Field Programmable Gate Arrays (FPGA).

FPGAs are high-density Programmable Logic Devices (PLDs) with, usually, more than a million gates and 100s of I/O ports.1 Most of the manufacturers of the FPGAs provide software to program these devices. Hardware Description Languages such as VHDL and Verilog, which were initially used to describe and simulate digital logic circuitry, are currently being used to implement complex algorithmic logic and then loaded into the FPGA.

Intellectual Property (IP) cores are reusable digital design functions that are provided by different organizations. These IP cores can be reused by either manufacturers or designers with little to no customization. This reduces the time for development and time to market new systems. The IP cores also serve as a powerful mechanism by which one industry can take advantages of developments in other industries. The use of IP cores relieves the engineers and researchers from the technical details of the systems that are outside their core areas, thus, helping them to focus on their core competence areas. As an example of this is that the control engineers can focus on the development of control algorithms while using a core for communication from a third party.

In the project reported on here the Proportional, Integral and Derivative (PID) controller is implemented on a Xilinx FPGA. The serial UART core from opencores.org2 is used for communication between the Men-Bradley’s MicroLogix 1500 LRP PLC and the FPGA. The performance of the PID controller that was implemented on the FPGA is compared to a PID controller implemented using software. The FPGA in this project serves as a configurable hardware unit used to implement computationally intensive algorithms. The FPGA works in conjunction with a PLC making the overall system highly responsive and configurable.

II. Experimental Approach

In this project a PID controller was designed and implemented on the Xilinx’s Spartan 3 XCS400 FPGA.An IP core from opencores.org was used for communication protocol. The FPGA is integrated with the PLC using serial communication. The FPGA receives PID parameters from the PLC and uses it to control a position control system. The PID controller, thus, relieves the PLC from computationally intensive operations.The implemented PID controller is compared against the standard approach of implementing the PID controller in the PLC’s ladder logic software.

The block diagram of the project is shown in Figure 1. A ladder logic program was written to transmit the PID parameters. The UART core on the FPGA receives the parameters and passes it to the PID controller for control. The analog-to-digital converter controller receives the feedback position from the serial ADC on board.The digital-to-analog converter receives the PID output to correct the error. The voltage output of the D/A converter is converted into current by a high-current high-voltage operational amplifier.

The details of the sub-systems are:

a) Position Control System: A position control system using two DC solenoids (Guardian, Model No. 4HD-C-12VDC) at the opposite ends connected by a single plunger was used to evaluate the PID controller.

Figure 2 shows a photograph of the position control system. The system has a damper (Airpot, S160A 15OF) mounted to provide additional stability to the system. This position control system has been used in control system courses at ASU to test various control techniques.3,4 Movement toward the left is controlled by the solenoid on the left, while moving to the right is controlled by the other solenoid. The position of the control system is controlled by controlling the current flowing through the solenoids’ coils.

b) Signal Conditioning: A linear potentiometer (Midori America, LP-50F), excited by a 5V DC source, converts the linear position into a corresponding voltage. The signal is conditioned by using a three op-amp (National Semiconductor’s LM324) instrumentation amplifier before feeding it as an input to the on-board analog to digital converter.

c) FPGA Development Board: Nu Horizon’s Spartan 3 Development board was used to implement the control algorithm and the serial communication protocol. VHDL code for the following modules were developed:

i) LCD Controller: The FPGA development board has has an on-board 4×20 character LCD display. LCD controller code was implemented to display PID parameters. The LCD controller also served as a visual debugger during development of other modules.

ii) UART core:The serial port in the FPGA is used to receive parameters from the PLC. Open source IP core from opencores.org2 with minor modifications was used in this project.

iii) PID controller: The PID controller was developed to implement the PID control algorithm. The analog form of the PID algorithm is given by:

where:

o(t) is the controller output

e(t) is the error between the set point and the measured output

Kp is the proportional gain,

Ki is the integral gain,

Kd is the derivative gain

The above equation can be re-written in discrete form by using the trapezoidal rule for integration and a four-point central-weighted average for the difference term5 as:

where R is the set point,

o(k) is the controller output

e(k) = R – C(k) = error

C(k) is the measured output at kth sampling time

T is the sampling interval

This equation was used in the implementation of the PID controller. It should be noted that a full floating point unit was not implemented and integer approximations are used during calculation.

iv) Analog to Digital Converter Controller: This module configures the serial Analog to Digital converter (ADC) LTC1864L and gets the current position. The ADC is a 16-bit ADC and is part of the development board.The module implemented as a state machine is driven by a clock rate of 6.25 MHz. The ADC module takes 69 clock cycles to collect one sample making the sampling period of the system 11.04 7micro;s.

v) Digital to Analog Controller: The DAC controller, implemented as a state machine, drives two 14-bit DAC MAX7538. The module sends the calculated output to one of the two DACs depending on the sign of the PID controllers’ output and zeros the other DAC input.

vi) Pulse Width Modulation (PWM) Module: The PWM module was implemented using the counter. The output was verified by viewing the signal on an oscilloscope. This module was implemented to just showcase the fact that multiple units can coexist in a single FPGA and did not serve any control purpose.

vii) A main unit instantiates all the VHDL units and coordinates exchange of data between various units.

d) Solenoid Driver:The solenoid driver circuit from previous projects4,6 was used for this project. The driver consists of the two, high-voltage, high-current operational amplifiers OPA549 (TI/Burr-Brown).The current to the solenoids’ coils are varied to control the position.

III. Results and Discussion

The execution times for the PID controller when implemented as a software module and as a FPGA module were compared.The time required to execute the ladder logic with the PID control algorithm by the PLC was found to be between 0.8 ms and 1.9 ms. This time was obtained from the system status file of the PLC.The PID control algorithm when implemented on a FPGA was found to be of the order of ns as determined from the synthesizer’s output. It should be noted that output was not directly measured because of the very high frequency. The low execution time of the FPGA based PID controller did not improve the overall system response by the same huge factor because the system was limited by other components, such as A/D converter, and mechanical system. However it should be noted that the FPGA based controller provides significant performance improvement if there are a large number of PID controllers or the system response time is high.

The entire system was simulated using MATLAB-SIMULINK. A square wave producing a positional change of +/0.2 inches is given as input to the system and the output is shown Figure 3.A detailed analysis of the system response using just the PLC is done in Macia & Susilo.4 It can be seen that the system behavior in both cases is only marginally different.

The PID control algorithm when implemented as an FPGA module takes much less execution time than the PID implemented on the PLC’s ladder logic software. The output was recorded using LabVIEW and the PCI 6024E data acquisition system. This is the result of the fact that the FPGA implements the PID controller in hardware. The output from one of the runs (Proportional feedback only) is shown in Figure 4 with position in mils and time in seconds. There are some errors evident in the figure because of mechanical alignment and friction effects.

The PID controller takes a few hundred nanoseconds to execute and produce the output. However in the current system the ADC’s sampling time was 11.0 µs and became the limiting factor in the entire system.

The PID controller unit was also tested separately by simulating the parameters. The output of the PID controller was fed directly to the D/A converter. The PID controller was able to produce output at the rate of 50 kHz.Thus it can be concluded that the implementation would be able to produce results within 20 µs, if not limited by the other components of the system.

To compare the cost between the traditional approach of using the PLC with an off-the-shelf discrete module and the PLC with FPGA, a hypothetical application involving a High Speed Counter is considered. The cost of the PLC along with a discrete, off-the-shelf, High Speed Counter module provided by vendor comes to around $1434.96 the breakdown of which is shown in Table 1. The PLC used in this comparison is the Alien-Bradley, Micrologix 1500LSP.

The component cost of the system when an FPGA module is used is illustrated in Table 2. In this implementation, a PLC with a system processor that has two serial ports is considered as one of the ports is used for communication with the FPGA module. Estimated, one-time development cost to implement the high speed counter function in the FPGA is shown in Table 3. It can be seen that the component cost associated with the PLC and FPGA system is 30% cheaper. The initial development cost is recovered after around 8 units, as indicated by the graph shown in Figure 5.

IV. Conclusion

The project clearly demonstrated the benefits of using an FPGA and a PLC together. This approach is ideal for processes which have a mix of both slow and fast control system elements. In such systems, industrial controllers control the slow control system and use the FPGA for the fast control systems. However, since most of the industrial control systems are slow and do not need a fast controller, the effect of such a combinational implementation will be most evident when implementing many simultaneous control loops. The controller implemented in this project can be easily multiplexed to implement multiple control loops.The presented approach can also be used by researchers to implement novel control algorithms. The project also highlighted the advantages of using IP cores for reusable functions. The use of an FPGA as part of a configurable system is a quite different than the conventional approach.To make this approach more acceptable to industrial users, customer training and software tools will need to be provided.

References

1. “Xilinx Home: Products and Services,” Xilinx 2003. Available HTTP: http://www.xilinx.com

2. Carton, E, “Project: Serial UART,” Opencores, 2003 Available HTTP: http://www.opencores.org/projects/miniuart2/

3. Macia, N. E, “Using a DC Solenoid in a Closed-loop Position Control System to Teach Control Technology,” Proceedings, 1996 ASEE Annual Conference, Washington, DC, 1996.

4. Macia, N.F., Susilo, S., “Dual DC-Solenoid, Closed-loop, Position Control System Implemented with a MicroLogix 1500 PLC,” Proceedings, 2006 ASEE Annual Conference, ASEE, Chicago, IL, 2006.

5. Gray, J.W., “PID Routines for MC68HC11K4 and MC68HC11N4 Microcontrollers,” Motorola, 1996. Application Note 1215 /D

6. Macia, N.F., Susilo, S. Modeling & Control of Dynamic Systems-Lab Manual. Clifton Park, Thomson Delmar Learning, 2005.

Narciso F. Macia

Narciso F. Macia is an Associate Professor in the Department of Electronic Systems at Arizona State University at the Polytechnic campus. He received B.S. and M.S. degrees in Mechanical Engineering in 1974 and 1976 from the University of Texas at Arlington. He also received a Ph.D. in Electrical Engineering from Arizona State University in 1988. In 1975, he joined Honey well (then AiResearch) and worked as a Development Engineer in the fluidics group until 1981. Afterward, he cofounded a small company to develop medical, fluidic devices. In 1990, he joined ASU, and has been teaching classes in electronics, instrumentation, control and prototype development. In the past, he has served as the Associate Chair in charge of electronics-related programs. He is active in fluidics, respiratory mechanics, water filtration and recharge, embedded control, entrepreneurship mentoring, sustainable technologies and innovative methods for engineering education. He is a Registered Professional Engineer in the State of Arizona.

Esaki Soundarajan

Esaki Soundarajan received his Masters degree in Computer Engineering Technology from Arizona State University East in 2005. He got his Bachelors Degree in Electronics and Instrumentation from Government College of Technology Coimbatore, Coimbatore, India. He served as an Instrumentation Engineer for 2 years in a petrochemical company in India. Soundarajan worked as a software consultant for 4 years, and is currently working with Intel Corporation as a software engineer in the Process Control Systems division. His primary research interest areas are software-based control systems and embedded systems.

Bruce R. Millard

Bruce R. Millard has been at ASU since 1982, when his Ph.D. studies commenced. His Ph.D. was awarded in 1986. In 1987 be joined the staff of the Engineering College as a Research Scientist.After a short break in 1988-1989 as a Senior Research Scientist at the GE Advanced Technology Laboratory, he returned to ASU as a Research Scientist in the Engineering College and Adjunct Faculty in the Computer Science department. In 1993, Dr. Millard became a Research Scientist in the ASU central Information Technology department as the department’s Chief Technologist. A year later, he was named Director of Systems Integration and Management in IT. Until 1998, he continued as Adjunct Faculty with Computer Science. In 2000, Millard joined what is now the ASU Polytechnic campus and is a professor in the Division of Computing Studies. His primary expertise is in operating systems and networking with a special interest in Cyber security. Millard’s vita, which includes publications, research, and student supervision, is available at http://ctas.east.asu.edu/millard

Cristian Sisterna

Cristian Sisterna, is an FPGA Hardware Engineer at Marvell Semiconductor Inc, with previous experience at Philips Semiconductor, Intel Corporation and Lattice Semiconductor. He previously was an Associate Professor at the National University of San Juan, Argentina. Sisterna obtained his Bachelor Degree in Electrical Engineering from National University of San Juan in 1987.In 1998, working as a as a Fulbright Scholar, he received his Master of Technology degree at Arizona State University Polytechnic campus. Sisterna has taught VHDL/FPGAs at both Arizona State University and National University of San Juan at graduate levels. He is an active collaborator with the Polytechnic Campus and has significant expertise in microcontrollers, and embedded systems.

Copyright AMERICAN SOCIETY FOR ENGINEERING EDUCATION Spring 2007

Provided by ProQuest Information and Learning Company. All rights Reserved