electrical characteristics of 4H-SiC Schottky diodes after inductively coupled plasma etching, The
Plank, N O V
The electrical characteristics of metal contacts fabricated on 4H-SiC have been investigated. Sputtered nickel ohmic contacts have been successfully produced on untreated 4H-SiC substrates and 4H-SiC surfaces cleaned with aggressive chemicals and ion sputtering. The current-voltage (I-V) characteristics of as-deposited contacts are observed to be nonohmic on all surfaces. After annealing at 1,000[degrees]C in a N^sub 2^ atmosphere, the contacts are seen to become ohmic with considerably less annealing time being required for the samples exposed to aggressive cleaning stages. Schottky diodes were then produced on the silicon carbide (SiC) surface after etching in an SF^sub 6^/O2 inductively coupled plasma (ICP) for 3 min at varying substrate bias voltages and also on an untreated surface used as a control sample. The ideality factors of all diodes formed on the etched surfaces increased in comparison to the control sample. The highest ideality factor was observed for the diodes produced after etching at -0-V and -245-V bias voltage. A two-diode and resistor model was applied to the results that successfully accounted for the excess leakage paths. The defect density of each SiC surface was calculated using both the measured and the simulated ideality factors. An annealing stage was successful at reducing the ideality factors of all the diodes formed. The defect density calculated using the measured ideality factors of the annealed diodes was seen to have been reduced by an order of magnitude.
Key words: Silicon carbide, ICP etching, Schottky diodes, ideality factor, model, defect density
(Received January 23, 2003; accepted June 1, 2003)
Silicon carbide (SiC) is a wide bandgap semiconductor that is known to be suitable for high frequency and high-power devices. The material strength and stability also make SiC a useful candidate for microelectromechanical systems technologies.1 However, it is due to the stability of SiC that high-density, plasma etching techniques, such as inductively coupled plasma (ICP) etching, are often required during device processing. It is possible that ICP etching can cause damage to the surface of the SiC substrates because of the high energy of the ions that bombard the surface, and the reactive radicals that are produced during the etching process. Defects may then be introduced into the semiconductor substrate crystal lattice,2 which can alter the properties of the semiconductor. Here, the effect of ICP etching in fluorinated plasma at a selection of substrate bias voltages has been investigated by the production of 4H-SiC Schottky diodes. To characterize the etch-induced damage on the substrate surface, the current-voltage (I-V) characteristics of the metal-semiconductor contacts are investigated. As a test of the quality of the diodes produced, the ideality factor and barrier height of the diodes are extracted with the use of the thermionic emission theory.3 Previous studies4,5 have used this method to investigate surface damage on semiconductor substrates. Here, the ideality factor as a function of voltage is considered, and a model similar to the model used by Defives et al.6 and Ellis and Barnes,7 which includes the voltage dependence of the ideality factor, is developed to fit the experimental data. Most current methods of diode characterization do not consider the effect of the ideality-factor voltage dependence. The model used provides a means of accounting for the current leakage paths present in diodes that are not displaying pure thermionic emission characteristics. Although the model is successful at accounting for the leakage paths, it offers no real physical insight into the origin of the deviations from ideality. An annealing stage has successfully reduced the ideality factors of all the diodes produced during this investigation, indicating that the origin of defects may be due to inhomogeneities between the metal/semiconductor interface, as was postulated during previous studies by Waldrop and Grant8 and Kestle et al.,9 which have also shown improvements of diode characteristics after annealing. However, it is possible that the improved characteristics may be due to defect migration and annihilation during the annealing stage.2
Two 4H-SiC substrates with nominal n-type doping of 1 x 10^sup 16^ cm^sup -1^ from Cree Research1 were used: wafer A with a resistivity of 0.448 [mu]-cm and wafer B with a resistivity of 0.3 [mu]-cm. The wafers were cut into 1-cm^sup 2^ pieces, which were prepared to produce the ohmic contacts. Wafer A was chemically cleaned in acetone and isopropyl alcohol (IPA), then dipped in a HCl:H2O, 1:1 solution for 5 sec before being immediately loaded into the Balzers sputtering machine (Balzers AG, liechtenstein (now Unaxis)). A 200-nm layer of nickel was then sputtered to produce a backside ohmic contact. The sample was then annealed in a nitrogen atmosphere at 1,000[degrees]C until the contact became ohmic. The samples from the second wafer were prepared differently. The substrate pieces were cleaned in fuming nitric acid, followed by acetone, and then IPA. After this, the samples were loaded into the Balzers sputtering machine. Immediately prior to metal deposition, the backside of the wafers was sputter cleaned with argon atoms for 5 min. A 200-nm layer of nickel was deposited onto the sputtered surface without breaking the vacuum. The samples were again annealed at 1,000[degrees]C in an N^sub 2^ atmosphere.
The Schottky diodes have all been formed onto samples from wafer B. After the formation of the ohmic contacts, the front side of the wafer surfaces was etched in the STS ICP reactor (Surface Technology Systems GmbH, Ulm, Germany) in a gas mixture of SF^sub 6^/O2, 40/10 seem, with an ICP coil power of 1,000 W and chamber pressure of 5.5 mtorr. The surfaces were all etched for 3 min at bias voltages of -0 V, -50 V, -95 V, -150 V, and -245 V. The diodes were patterned onto the etched surfaces of the samples using optical lithography and then dipped in an HCl:H2O, 1:1 solution for 5 sec prior to 100 nm of aluminum being deposited using the Edwards thermal evaporator. After liftoff in acetone, 100-[mu]m^sup 2^ diodes remained. Using the HP 4165B probe station (Hewlett-Packard Company, Palo Alto, CA) and software from ICCAP (Integrated Circuit Characterization and Analysis Program, Agilent Technologies, Palo Alto, CA), the I-V characteristics of the ohmic contacts and the Schottky diodes were obtained. Typically, three diodes on each sample were tested to ensure that the I-V characteristics obtained were consistent across the samples.
RESULTS AND DISCUSSION
The deposition of Ni at room temperature followed by annealing at approximately 1,000[degrees]C in a N^sub 2^ atmosphere is the most common way of forming ohmic contacts to SiC. The physics of the interaction is still not fully understood, although it is known that a metal suicide will form, usually in the form of Ni^sub 2^Si.10 The I-V characteristics of the ohmic contacts were measured using the HP 4165B probe station using the lateral, two-terminal contact method.11 The I-V characteristics of ohmic contact A (Fig. 1) measured after annealing at 1,000[degrees]C in an N^sub 2^ atmosphere for 18.5 min show that the as-deposited contacts are not ohmic, but as the annealing time is increased, become progressively more ohmic in nature.
The ohmic contacts produced onto wafer B (Fig. 2) also show improved ohmic behavior; however, the ohmic contacts produced on wafer B only required 15 sec of annealing to become ohmic. The results show that the ohmic contacts formed on samples that have been subjected to aggressive cleaning agents and high-energy ion bombardment require significantly less annealing time to become ohmic.
The I-V characteristics of the aluminum diodes produced on the front side of the wafer were measured using the HP 4156B probe station and ICCAP software. The I-V plots show that all the diodes fabricated are clearly rectifying (Fig. 3a). Table I contains the reverse leakage currents of each diode. The diodes on any one sample all exhibited similar behavior with reverse leakage currents and turn-on characteristics all lying at close to the same value. For example, for the unetched diode at -30 V, I = -2.88 x 10^sup -7^, and [sigma]^sub n^ = 0.1 x 10^sup -7^. The I-V characteristics shown are for one diode produced on each sample.
All of the reverse leakage currents are relatively low up to the maximum voltage tested here of -30 V, and it can be seen that no breakdown has been detected up to this point. Because of the material properties of SiC, breakdown is not expected until much higher voltages are applied. Other authors have found breakdown voltages of 4H-SiC diodes in excess of -1,000 V.12 The diodes produced at -0 V and -245 V have the highest leakage currents over all voltages. The leakage currents increase with etching bias voltage, excluding the diode formed at -0 V where the high leakage current is believed to be due to surface modification. The presence of oxygen-related defects has previously been observed to alter current transport mechanisms.13 At low etching bias, the ion energies may be insufficient to accelerate the chemical reactions at the surface, leading to fluorocarbon or oxygen saturation. The observed trend of increasing etching bias producing increased leakage currents is attributed to the increased ion energies causing physical damage to the surface, as was found in a study by Cho et al.,14 where lattice damage was introduced when ion energies exceeded 60 eV. To test the quality of the Schottky diodes, the ideality factors, [eta], were calculated using the thermionic emission theory3 as follows:
The ideality factors of all the diodes produced on the etched surfaces deviated significantly from the control sample. The ideality factor as a function of voltage (Fig. 3b) shows that the ideality factor does not remain constant and is increasing with V.
Similar to the reverse leakage observation, the worst diode is again seen to be produced after etching at -0 V, as found during other studies,16 followed by the diode formed at -50 V and at -245 V, thus leading to the conclusion that strong deviations from ideality can be due to either chemical deposition or ion-induced lattice damage. The high ideality factors found imply that the current transport mechanism is not pure thermionic emission. There are excess leakage currents traveling through the diodes.
Modeling Techniques: The Series and Parallel Models
To account for the voltage dependence of the ideality factor, a model consisting of a diode and a resistor in series (Fig. 4a) was used. This model was also extended to contain two diodes and two resistors in parallel in order to include an additional current leakage path (Fig. 4b) and is similar to models used in previous diode analysis of GaAs Schottky diodes and Ti/6H-SiC Schottky diodes.6,7 The models were fitted to the measured data using HSPICE (Unix-based Simulation Program for Integrated Circuits Emphasis, Synopsis, Inc., Mountain View, CA) and ICCAP.
The ideality factors and the resistances extracted using the series model are given in Table II, where the saturation currents are taken from the measured data. The simulated data from the series model is seen to be a poor fit to the measured (Fig. 5). Although the series model has been successful at considering the voltage dependence of the ideality factor, the model has not allowed for the leakage currents to be considered separately to the ideal path. To account for the leakage paths, the parallel model was then applied to the results.
The ideality factors and saturation currents of the leaky diodes extracted from the parallel model are given in Table III, where the upper diode parameters and the lower diode resistances were held constant throughout the simulation. The upper diode ideality factor is 1.07, which was the measured ideality factor of the control diode produced on the unetched surface, for all diodes except that produced after etching at -245 V, where an ideality factor of 2.02 was required to fit the data. The saturation current and resistance of the ideal path had little effect on the simulation, so it was reasonable to hold these parameters constant. The parallel model provided a means of accounting for the voltage dependence of [eta], as well as the additional current leakage paths for the diodes fabricated on etched SiC surfaces.
Figure 6 shows the good fit obtained between the simulated and the measured currents using the parallel model, as this model has successfully accounted for the excess leakage current of the Schottky diodes, unlike the series model. As was the case with the measured data, there is no linear correlation observed between the barrier height (which corresponds to the saturation current by Eq. 3) and the ideality factors of the diodes. The worst diode is again seen to be the diode produced after etching at -0 V. The saturation currents deduced from the parallel model are approximately the same as the measured values with the exception of the diodes produced at -0 V and -50 V, where the simulated saturation current in both cases is one order of magnitude higher than the measured value.
The simulated ideality factors from the parallel model, when considered alone, imply that the introduction of energetic ion bombardment can initially improve the diode ideality, most likely, because of the removal of deposited polymers. However, when the ion bombardment energy is increased too far, here at -150 V, the ideality factor again increases. Although the leakage path ideality factor at -245 V does not agree with this hypothesis, the ideal path does not have an ideality factor close to unity, suggesting that this diode has many defects.
The saturation currents of the lower diodes deduced by the parallel model indicate that the chemical deposition at -0 V has led to the formation of a poor quality diode. After etching at -50 V, however, the saturation current is of the order of ICT11 A, which is also the case after etching at -245 V. The saturation currents at the intermediate bias voltages of -95 V and -150 V are higher at 10^sup -9^ A and 10^sup -8^ A, respectively, showing that the saturation current is seen to rise and fall. Because of the nature of plasma etching, the etch rate at the different bias voltages tested will have been different, and the surface chemistry of each diode may have been altered significantly between diodes. The saturation currents deduced here indicate that the defects present are different and imply that the substrate surfaces will have reached different stages of the reaction at each point.
The models used have allowed for the voltage dependence of the ideality factors and, in the case of the parallel model, considered the leakage current paths. However, neither model has offered any physical insight into the origin of the leakage paths of the Schottky diodes. Surface analysis techniques, such as x-ray photoelectron spectroscopy (XPS), would provide a means of further characterizing the origin of the leakage paths. It is predicted that these leakage paths are caused by a combination of the creation of defects and chemical changes. As a means of improving the deviations from ideality, an annealing stage was applied to the Schottky contacts.
Annealing the Schottky Contacts
The annealing of the sample allows the semiconductor and the metal to form a more intimate contact, similar to the annealing of ohmic contacts. The samples were annealed in a furnace at 400[degrees]C in an N^sub 2^ atmosphere for 5 min, followed by a H^sub 2^/N^sub 2^ atmosphere for 10 min, and finally, in N^sub 2^ for a 5-min purge stage. After annealing, the I-V characteristics were again measured, and the ideality factor and barrier heights extracted. These are shown in Table IV.
It is seen that the barrier height has increased for all of the diodes formed, while the ideality factors have decreased. At first sight, this implies that the diodes have all been improved. The ideality factors as a function of voltage are shown in Fig. 7. It is seen that the ideality factor increase with voltage is less extreme than the rise observed for diodes prior to annealing. The reverse leakage currents, which are shown in Table V, have also improved with the exception of the diode produced at -95 V. The most dramatic change has been of the sample etched with a direct current bias of -0 V, an etch condition dependent upon the chemical reactions, as there is only the built-in plasma potential and no applied-substrate chuck bias present. The ideality factor at 0.25 V has decreased from 4.057 to 1.313 for the annealed diode.
Similar studies for which diodes have been annealed after the metal deposition have also shown improved ideality factors.4,9,15,17 The improvements to the ideality factor are attributed here to the reduction of barrier inhomogeneities caused by the annealing. With a more uniform, intimate contact, leakage paths will be reduced and emission over the barrier will dominate the current transport.
The success of the annealing stage of a Schottky diode will depend on the surface chemistry and roughness of the sample surface, as it did for an ohmic contact. The temperature and the crystal face of the substrate surface have previously been shown to affect the annealing stage for Ni and Ti contacts in a study by Waldrop and Grant.8 The study showed that Al contacts have a similar limited reaction to both the Si face and the C face with the annealing temperature at 600[degrees]C. The chemistry of the annealed contact varies depending upon the thickness of the metal deposited and the temperature of the anneal; probe techniques, such as XPS, are required to uncover the reaction mechanism here. Work carried out by Kestle et al.9 have used XPS on Ni/SiC Schottky diodes. Improvements to the ideality factor after annealing were shown to be temperature dependent, where the diodes annealed at 500[degrees]C were ideal, good rectifiers, while those annealed at 600[degrees]C were poor rectifiers.
The surface chemistry of the etched surfaces may be significantly affecting the ideality of the diodes. In a previous study by Castaldini et al.,13 a non-homogeneous interface between the metallization and the substrate, mainly caused by oxygen-related defects, has been observed to cause alterations to the current transport mechanism. The annealing step may have reduced the effect of similar defects on the etched SiC surface.
It is also necessary to consider the effect that the annealing stage may have had on the etch-induced defects within the semiconductor crystal lattice. The defect migration taking place during the annealing stage could have caused the defect density to reduce by annihilation.2 However, it could also be the case that defect migration could cause defects to combine and, hence, increase the defect concentrations. The orientation of the sample during the etching stage could also have affected the presence of the ion channeled defects.18 Further experiments are required to investigate all of these options.
Defect Density Calculations
In a study of Si Schottky diodes by Sung et al.,19 the ideality factors and Schottky barrier height were used to calculate the defect density produced after etching at different bias voltages. When considering the ideality factor, the defect density can be calculated as in Eq. 5 (see at bottom of the page),19 and when considering the Schottky barrier height, the defect density is calculated by
where E^sub g^ is the bandgap energy of SiC, A* is the Richardson constant, [tau]^sup -1^ is the injection rate, and [straight phi]^sub b-c^ is the difference between the metal work function and the semiconductor electron affinity, in this case, the metal work function of Al = 4.2 eV^sup 3^ and the electron affinity of SiC = 4.12 + or – 0.04 eV.20 The defect density calculated using Eq. 5, after etching at each bias voltage, are shown in Fig. 8 for the original diodes, the diodes simulated using the parallel model, and the annealed diodes.
The defect density calculated using the measured ideality factor and the simulated ideality factor show a similar trend (Fig. 8), whereby increases and decreases of the defect density occur for the same diodes. However, by using the measured values of the ideality factors, the defect density is observed to fluctuate more dramatically. Looking at the simulated data alone, there is an overall reduction in the defect densities from -0 V to -245 V with the exception of the diode produced at -95 V; at which point, there is a significant drop in defect density over all other diodes. The reduction of defect density for the simulated values, discounting the diode at -95 V, follows a steady curve with only a slight overall reduction in defect density. The measured data also shows an overall decrease in defect density from -0 V to -245 V. However, there is no steady trend observed, and the defect density varies significantly from one diode to the next with reductions occurring at both -95 V and -150 V. During the investigation by Sung et al.,19 the defect density was seen to drop to zero after 60 nm had been removed from the etched surface. Here, the results show that a reduction of defects has occurred at -95 V, again implying that etching at -95 V is the most likely etching bias to be useful for improving the diode characteristics.
The defect densities of the annealed diodes have been calculated using Eq. 5. The defect densities have been considerably reduced for the annealed diodes in comparison to the original diodes produced at all bias voltages. Across the annealed diodes, the defect densities remain relatively constant in comparison to the diodes prior to annealing and the simulated data. There is no significant defect density drop at -95 V, although the defect density is low at this point. The most dramatic reduction of defect density is observed at -0 V and -50 V. It is possible to conclude that the annealing stage has reduced the presence of defects within the crystal lattice by either annihilation or reduction of the barrier inhomogeneities; both of which would have a similar effect on the calculated defect densities.
By using the second method of calculating the defect densities (Eq. 6), no further insight has been provided as over all bias voltages N x [tau] [asymptotically =] 1.21538 x 10^sup 25^cm^sup -2^ s for the original measured results, the simulated data, and the annealed data. Further experiments involving calculation of the electron affinity of 4H-SiC at this doping may be required along with more experimental data, such as capacitance-voltage measurements and refinements to the model, to gain an accurate indication of the defect density using the Schottky barrier heights. A model that can successfully calculate the defect densities using the Schottky barrier height may provide further insight into the method of improvement present during the annealing stage.
At present, it is reasonable to conclude that the role of the annealing stage has been mostly to improve the metal-semiconductor contact by reducing barrier inhomogeneities. This is due to the structure of the SiC crystal lattice causing ion-channeling defect introduction to be less likely than for other semiconductors, such as gallium arsenide and silicon, which have crystal structures that allow more readily for ion channeling to take place and for which this effect has been previously observed. Further investigations involving SiC substrates are required. Surface chemistry is also expected to play a significant role in determining the quality of the Schottky diodes produced here because of the poor characteristics of the diode produced at -0 V. Experiments involving XPS surface probes are necessary.
It has been shown that the behavior of nickel ohmic contacts on SiC can be improved with the use of a high-temperature annealing stage. Shorter annealing times are required to produce ohmic contacts on surfaces that have been treated with aggressive cleaning techniques.
The influence of the bias voltage on reverse leakage current and ideality factors of Schottky diodes indicates the presence of etch-induced damage on the substrate surface, more so at -0 V and -245 V. The parallel model applied to the I-V measurements of the diodes has allowed for the ideality factors to be calculated, taking into account the voltage dependence of the ideality factor and the existence of an additional leakage current path. The simulated data shows that the relationship between the etching conditions and the quality of the diodes is nonlinear, indicating that the complex surface interactions that take place during the plasma-etching process have led to improvements at -95 V over all other etching conditions. Although the model is successful at accounting for current leakage paths, it offers little physical insight into why the leakage paths occurred. By annealing the Schottky diodes, the ideality factors were all found to decrease, thus implying that the deviations from ideality are due to inhomogeneous contacts. The diode produced on the sample etched at -0 V bias voltage has responded most significantly to the annealing stage. The defect densities, calculated using the measured ideality factors of the original diodes and the simulated ideality factors using the parallel model, have shown a significant drop in defect density at -95 V. In addition, the defect densities calculated from the ideality factors of the annealed diodes have improved by an order of magnitude in comparison to the same diode prior to annealing.
1. Cree, Inc., Durham, NC, http://www.cree.com.
2. M. Rahman, J. Appl. Phys. 82, 2215 (1997).
3. S.M. Sze, Physics of Semiconductor Devices, 2nd ed. (New York: John Wiley & Sons Inc., 1981).
4. F.A. Khan, B. Roof, L. Zhou, and I. Adesida, J. Electron. Mater. 30, 212 (2001).
5. D.J. Morrison, A.J. Pidduck, V. Moore, P.J. Wilding, K.P. Hilton, M.J. Uren, C.M. Johnson, N.G. Wright, and A.G. O’Neill, Semicond. Sci. Technol. 15, 1107 (2000).
6. D. Defives, O. Noblanc, C. Dua, C. Brylinski, M. Bathula, V. Aubry-Fortuna, and F. Meyer, IEEE Trans. Electron. Dev. 46, 449 (1999).
7. J.A. Ellis and P.A. Barnes, Appl. Phys. Lett. 76, 124 (2000).
8. J.R. Waldrop and R.W. Grant, Appl. Phys. Lett. 62, 2685 (1993).
9. A. Kestle, S.P. Wilks, P.R. Dunstan, M. Pritchard, and P.A. Mawby, Electron. Lett. 36, 267 (2000).
10. J. Crofton, L.M. Porter, and J.R. Williams, Phys. Status Solidi (b) 202, 581 (1997).
11. D.K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. (New York: John Wiley & Sons Inc., 1998).
12. G. Pope and P.A. Mawby, Proc. 23rd Int. Conf. Microelectron. Part 1, 181 (2002).
13. A. Castaldini, A. Cavallini, L. Polenta, F. Nava, C. Canali, and C. Lanzieri, Appl. Surf. Sci. 187, 248 (2002).
14. H. Cho, P. Leerungnawarat, D.C. Hays, S.J. Pearton, S.N.G. Chu, R.M. Strong, C.M. Zetterling, M. Ostling, and F. Ren, Appl. Phys. Lett. 76, 739 (2000).
15. S.K. Lee, C.M. Zetterling, and M. Ostling, J. Appl. Phys. 87, 8093 (2000).
16. L. Binghui, C. Lihui, and J.H. Zhao, Appl. Phys. Lett. 73, 653 (1998).
17. B.J. Skromme, E. Luckowski, K. Moore, S. Clemens, D. Resnick, T. Gehoski, and D. Ganser, Mater. Sci. Forum 338-342, 1029 (2000).
18. R. Germann, A. Forchel, M. Bresch, and H.P. Meier, J. Vac. Sci. Technol. B 7, 1475 (1989).
19. K.T. Sung, S.W. Pang, M.W. Cole, and N. Pearce, J. Electrochem. Soc. 142, 206 (1995).
20. L. Magafas, N. Georguolas, and A. Thanailakis, Semicond. Sci. Technol. 7, 363 (1992).
N.O.V. PLANK,1,2 LIUDI JIANG,1 A.M. GUNDLACH,1 and R. CHEUNG1
1.-Scottish Microelectronics Centre, School of Electrical Engineering and Electronics, University of Edinburgh, Edinburgh EH9 3JL, UK. 2.-E-mail: email@example.com
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