Intel Details Deerfield Processor, Rejiggers Roadmap

Mark Hachman

Intel continued to apply pressure to its competitors by disclosing that it would pull in a next-generation Xeon processor as well as forthcoming Itaniums.

Following the recent disclosure that the company would ship the dual-core Montecito in 2004, Intel said it would pull in a selected version of the Xeon DP, and add its first 90-nm Xeon core, Nocona, in the fourth quarter of this year. The company also provided detailed information on the “Deerfield” version of the Itanium processor.

However, system administrators at Intel’s customers will likely be most impressed by “Granite Peak,” a code name for an Intel initiative to slow down the driver revisions to one per every six quarters. Intel executives said IT managers have been asking for this feature to cut down on the amount of qualification each company has to do on Intel’s new chipsets.

“One of the things we deal with as a company is the stabiliity of the (disk) image,” said Louis Burns, vice president and general manager of Intel’s Desktop Products Group.

That will mean that Intel won’t issue another major driver revision until after the Prescoot processor ships, and the Dothan processor considered the mobile version of Prescott, next year, barring a major calamity. “I won’t say it’s set in stone,” said Jeff McCrea, director of corporate client demand, in an interview. “Maybe hard rubber.”

For now, however, manufacturing is the watchword. Throughout the last few months, Intel executives have emphasized the company’s steady march to 90-nm even as competitors have stumbled on extending the life of existing processors on 130-nanometer (0.13-micron) parts. Tuesday, company executives said the company’s fabs are firing on all cylinders. In related news, Intel decided to retool its Chandler, Ariz.-based fab to produce 300-mm wafers rather than build a new one.

“I used to work at Intel, and the one thing I can say for them is that they’re conservative in their engineering,” said Joe d’Elia, director of market intelligence services for iSuppli. “If Intel says they’re in production at 90 nanometers, you can believe them.

Intel may not be first to sample 90-nm products, d’Elia said. “But I’ll bet they’re the first to production on 90 nanometers,” he said.

Bringing a processor from design to production usually requires eighteen months, said Lisa Graff, director of enterprise processor marketing for Intel. Instead, the company has been able to accelerate the design time on the established 130-nm process to only nine months.

In the third quarter of 2003, Intel will manufacture a two-way Xeon with a full megabyte of level-2 cache, using the now-standard 533-MHz bus. Nocona, a 90-nm dual-processor Xeon which also includes a 1-Mbyte cache, will be introduced in the fourth quarter at an undisclosed “increased” frequency, Graff said. “Lindenhurst”, a chipset fro two-way “Nocona” servers, will be introduced in 2004.

In 2004, all of Intel’s enterprise chipsets will use PCI Express, executives said.

Intel also added a few more details to its multiprocessor Xeon roadmap, including the inclusion of a “Gallatin” processor with 4 Mbytes of level-3 cache in the first half of 2004. Like the Gallatins produced in the second half of 2003, the Gallatin MP will be manufactured at a clock speed greater than 2 GHz.

“Potomac”, a new Xeon MP derivative likely built on the Prescott architecture, will debut in 2004 using a 90-nm process. Details of the Potomac, such as cache size and clock speed, were left undisclosed.. An Intel spokeswoman said that the Potomac would be backwards compatible with the existing Gallatin chipsets, but also plug into a new, specially designed chipset offering, “Twin Castle”.

Deerfield, now known as the Low Voltage (LV) Itanium 2, will be introduced in 2003. The chip will cut the Itanium’s power down to 62 watts, less than half of the 130 watts of maximum thermal power that the Itanium 2 and Madison have been specified to. Deerfield will initially ship at 1.0 GHz, using 1.5 Mbytes of level 3 cache and a 0.13-micron design process.

Copyright © 2004 Ziff Davis Media Inc. All Rights Reserved. Originally appearing in ExtremeTech.

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