Artificial intelligence based three-phase unified power quality conditioner

Moleykutty George

INTRODUCTION

The better controllability, higher efficiency, higher current carrying capability, and fast switching characteristics of static power converters are promoting major changes in controlling the power flow of transmission and distribution systems. On the other hand the nonlinear characteristics of these switching devices introduce many undesirable features such as low power factor, poor voltage regulation, zerosequence currents, imbalances, and harmonics. Traditionally passive filters, synchronous condensers, capacitors, and phase advancers were used to improve the power quality. The undesirable features such as lower efficiency, bulkiness, fixed compensation, resonance, and electromagnetic interference of traditional compensators urged power electronics and power system engineers to develop an adjustable and dynamic solution for power quality problems. Active power filters (APF) were introduced in order to compensate reactive power, to cancel current harmonics, to correct current imbalances and to control zero-sequence currents (1)-(12), where as the disturbances in terminal voltages shall be compensated using dynamic voltage restorer (DVR) (13)-(17). More recently UPQC has been introduced as a one shot solution to improve power quality. A multilevel converter using diode-clamped inverters that can handle higher voltages with extra degrees of freedom in the form of redundant voltage states has been proposed in (18). A new topology and control circuit proposed in (19) has been successfully tested for various operating conditions. In (20) authors have identified and tested new functionalities such as elimination of voltage sags resulted from short circuits. A new methodology for the evaluation and control of losses taking place in a UPQC has been proposed in (21). A new control strategy aimed to compensate reactive power, negative sequence current, current harmonics and also to regulate any voltage imbalance has been proposed in (22). A neural network controlled UPQC without injection transformer has been designed and reported in[23]. Another control structure (24) using linear quadratic regulator (LQR) along with hysteresis control is successfully tested for various operating conditions. UPQC implemented in (25) uses a control circuit without reference calculation. Complicated control structures of UPQC (17)-(25) have been replaced by a simple control technique in (26). Voltage interruption can also be eliminated by the use of a unified power quality conditioner with distributed generation (27). Recent research shows that AI based controllers are very promising in the field power system and power electronics (28)-(49). In (29) and (34) the conventional PI controller is replaced by a fuzzy logic controller [FLC] for the determination of the reference current in a shunt active power filter. Reference (32) shows the successful application of FLC to generate the switching signals required in an active filter realized using current controlled PWM inverter. In (37), T-S fuzzy model is used to predict future harmonic compensating current in an APF system. Successful application of artificial neural network (ANN) controllers for the implementation of APF system has been reported (38)-(47) and many disadvantages of conventional controllers could be eliminated by the use of ANN controllers.

In this paper UPQC has been proposed for the cancellation of harmonic currents, to compensate reactive power, to eliminate voltage harmonics, to improve voltage regulation, to correct voltage and current imbalances and to avoid voltage interruption.The novelty of this paper lies in the application of NNC algorithms such as MRC, and NARMA- L2 control to generate switching signals for the series compensator of the UPQC system. The control strategies of UPQC are detailed in second part of this paper. Simulation results in the third part illustrate the successful implementation of UPQC using NARMA-L2 and MRC.

UPQC WITH INTELLIGENT CONTROLLERS

Principle of UPQC: UPQC is one of the custom power devices used at the electrical power distribution systems to improve the power quality of distribution system customers. UPQC could be used to cancel current harmonics, to compensate reactive power, to eliminate voltage harmonics, to improve voltage regulation, to correct voltage and current imbalances, to correct voltage sag or swell and to avoid voltage interruptions. A UPQC consists of both shunt and series compensators. A shunt compensator is used to cancel the disturbances in current whereas series compensator is used to cancel disturbances in voltage. Shunt compensator could be connected to the left or right of the series compensator. Ideally, shunt compensator injects current to achieve purely balanced sinusoidal source currents in phase with the supply voltages at rated magnitude and frequency. On the other hand series compensation is used to inject voltage to maintain terminal voltage at rated magnitude and frequency.

Control circuit of UPQC: A three-phase system has been selected to study the performance of the UPQC system. (Fig. 1) shows the schematic diagram of the UPQC system. Voltage source inverters are used for shunt and series compensation. One may note that both voltage source inverters are supplied from a common dc link capacitor. One of the voltage source inverters is connected in parallel with the a.c. system while the other one is connected in series with the a.c. system through injection transformers. The inverter connected in parallel, together with its control circuit forms the shunt compensation circuit. On the other hand the inverter connected in series with appropriate control circuit forms the series compensation circuit. For the successful operation of the UPQC, the dc capacitor voltage should be at least 150 % of maximum line-line supply voltage. To regulate the capacitor voltage constant, either a PI controller or a fuzzy controller could be used. Thus the control structure of UPQC has been divided into shunt compensator and series compensator control circuits.

[FIGURE 1 OMITTED]

Shunt compensation control circuit: A current controlled VSI connected in parallel to the source through booster inductors functions as the shunt compensator. (Fig. 2) shows the block diagram of the control circuit of the shunt compensator (11). The control circuit consists of a voltage control loop and two current control loops. The ideal requirements of the shunt compensator circuit are (i) to maintain the capacitor voltage at a constant steady value and (ii) to maintain the source current purely sinusoidal in nature and in phase with the supply voltage.

[FIGURE 2 OMITTED]

a) Voltage control loop: The voltage control loop is used to determine the amplitude of the reference source current. Under steady state conditions the d.c. load removes energy from capacitor at constant average rate and the capacitor voltage can be maintained constant only if the incoming power from the a.c. side is equal to the output power demand. Thus the variation in capacitor voltage is a measure of the amplitude of the reference current. The voltage control loop senses the voltage across the capacitor, increases the current drawn from the supply if the capacitor voltage tends to decrease from the reference value and decreases the current drawn from the ac side when the capacitor voltage tends to increase. Thus the voltage control loop monitors the output voltage and determines the amplitude of the source current. The amplitude of the reference source current could be evaluated as follows:

[I.sub.max] = [G.sub.C]([V.sub.dcr] – [V.sub.dc]) (1)

where [G.sub.C] represents a PI or fuzzy controller.

Implementation Using PI Controller: According to stability criteria, the following relations may be used to determine the value of [K.sub.p] and Ki and of the PI controller.

[I.sub.s][less than or equal to][[[C.sub.D][V.sub.dcr]]/[3[K.sub.P][L.sub.s]]] (2)

[I.sub.s][less than or equal to][[[K.sub.p]Vcos[empty set]]/[2[R.sub.s][K.sub.p] + [L.sub.s][K.sub.i]]] (3)

Where V – supplyvoltage/phase(V)

[V.sub.dcr] – reference dc voltage(V)

[C.sub.D] – dc link capacitor value(F)

[R.sub.s] – source resistance([ohm])

[L.sub.s] – source inductance(H)

cos[empty set] – source power factor

[I.sub.s] – supply line current(A)

With these stability limits satisfied, the PI controller will maintain the capacitor voltage at the constant reference value and the output of the PI controller is in fact a measure of the amplitude of the reference supply current.

Implementation Using Fuzzy Logic Controller: A fuzzy logic controller uses linguistic variables instead of numerical variables. The internal structure of FLC is shown in (Fig. 3). Fuzzy inference process mainly consists of three steps namely fuzzification of the input variables, determination of the membership function (MF) graph for the output variable, and finally defuzzification of the linguistic output variable.

[FIGURE 3 OMITTED]

(i) Fuzzification of the input variables: In the fuzzification stage numerical values of the variables are converted into linguistic variables. Seven linguistic variables namely NB (negative big), NM (negative medium), NS (negative small), ZE (zero), PS (positive small), PM (positive medium), and PB (positive big) are assigned for each of the input variables and output variable. Normalized values are used for fuzzy implementation. As there are seven variables for inputs and output there are 7 x 7 = 49 input output possibilities as tabulated in Table. 1. A membership function value between zero and one will be assigned to each of the numerical values in the membership function graph. The membership function graph can have different shapes triangular, trapezoidal or gauzzian etc. For simplicity triangular membership function graph is chosen for the system under study.

Table 1: Control rule table

Error (e)

Change in error(ce) NB NM NS ZE PS PM PB

NB NB NB NB NB NM NS ZE

NM NB NB NB NM NS ZE PS

NS NB NB NM NS ZE PS PM

ZE NB NM NS ZE PS PM PB

PS NM NS ZE PS PM PB PB

PM NS ZE PS PM PB PB PB

PB ZE PS PM PB PB PB PB

(ii) Determination of the MF graph for the output variable: Consider the situation with error in capacitor voltage (e) equals 0.2 per unit and change in error (ce) 0.6 per unit. e = 0.2 per unit is having a membership function value of 0.1 in the ZE membership function curve and 0.6 in the PM membership function graph. The change in error 0.6 per unit has a membership function value of 1 in the PS curve. With e in the ZE membership function curve and ce in the PM curve will be in the PM membership function curve as indicated in Table. 1. Application of Mamdani implication method will result in a degree of fulfillment equals the minimum of 0.1 and 1 which is equal to 0.1 as shown in (Fig. 4(a)).

Similarly when e equals PS and ce equals PM then [[delta]I.sub.m] equals PM and will have a degree of fulfillment of 0.6 as shown in (Fig. 4(b)). The union of the above two output MF graphs (Fig. 4(a)) and (Fig. 4(b)) gives the final MF graph for the output as shown in (Fig. 4(c)).

[FIGURE 4 OMITTED]

iii) Defuzzification of the linguistic output variable: In the defuzzification stage the fuzzy output will be converted into a numerical value. Mean of maxima method (MOM) is used for defuzzification. In the MOM the highest membership function value of 0.6 is selected. Selecting three different points will give a final numerical output value of

[delta][I.sub.max] = [M.summation over (m = 1)][[[delta][I.sub.max m]]/M] = [0.7/3] + [1/3] + [1.75/3] = 1.15

Thus when e = 0.2 p.u. and ce = 0.6, [delta][I.sub.max] equals 1.15 p.u.. Thus output of the fuzzy controller gives the change in reference current [[delta]I.sub.max] (n) at the nth sampling time. The peak reference current [I.sub.max] (n) at the nth sampling time is determined by adding the previous reference current [I.sub.max] (n-1) to the calculated change in reference current:

[I.sub.max](n) = [I.sub.max](n – 1) + [delta][I.sub.max](n) (4)

In classical control theory this is an integration effect.

b) Current control loops: Ideally, shunt compensation is used to achieve a purely sinusoidal current wave form in phase with the supply voltage. The voltage control loop cannot ask the shunt compensation control circuit to draw the required power at an arbitrary current wave shape. It is the current control loop that makes sure that the supply current has the desired shape and amplitude as commanded by the voltage control loop.

Estimation of reference current templates: A phase locked loop (PLL) could be used to generate a unit amplitude wave form in phase with the supply voltage. The reference source current is obtained by multiplying the amplitude determined by the voltage control loop with the unit amplitude waveform generated by the PLL. The difference between the instantaneous source and load currents gives the reference compensation currents.

Hysteresis current controller: A hysteresis current controller [HCC] is used to generate switching pulses required for the VSI. In a hysteresis controller the reference compensation current is compared with the actual current that is being injected by the compensation circuit. A positive pulse is produced if the actual current tends to decrease below the lower hysteresis limit, while a negative pulse is produced if the current exceeds the upper hysteresis limit. Thus in a hysteresis current controller the actual compensation current is forced to stay within a particular hysteresis band.

2) Series compensation control circuit:

a) Conventional Techniques: A DVR based on a pulse-width modulated (PWM) VSI, which is capable of generating or absorbing real and reactive power independently at its ac output terminals is used as the series compensator. The series compensator injects three single-phase ac voltages in series and in synchronism with the upstream voltages in the distribution system. The power circuit could be divided into two main parts: three-phase VSI, three single-phase injection transformers. The three single-phase transformers are connected to the distribution system with a star/open winding. The star/open winding allows the injection of positive, negative and zero sequence voltages. The windings on the inverter side are connected in delta through inductors to provide high voltage. The block diagram of a series compensator is shown in (Fig. 5). Using Park’s transformation actual receiving end voltages ([V.sub.ra], [V.sub.rb], and [V.sub.rc]) may be decomposed into stationary axes as follows:

[V.sub.d] = [square root of [2/3]]([V.sub.ra]Cos[theta] + [V.sub.rb]Cos([theta] – 120[degrees]) + [V.sub.rc] Cos([theta] – 240[degrees])) (5)

[V.sub.q] = – [square root of [2/3]]([V.sub.ra]Sin[theta] + [V.sub.rb]Sin([theta] – 120[degrees]) + [V.sub.rc]Sin([theta] – 40[degrees])) (6)

[V.sub.0] = [square root of [2/3]](1/[square root of 2][V.sub.ra] + [1/[square root of 2]][V.sub.rb] + [1/[square root of 2]][V.sub.rc]) (7)

It has been found that to obtain line-line voltages of 400 V, [V.sub.dref] = 400 V; [V.sub.dref] = 0 V; & [V.sub.0ref] = 0 V. PWM technique is used to generate switching patterns for the VSI’s. Using abc to dq0 and dq0 to abc transformation, the receiving end voltage is regulated at 400 V rms by means of a PI controller.

b) Neural network control algorithms: The learning ability, self-adapting, and super-fast computing features of ANN controllers make it well suited for the control of power electronic circuits. In learning process, neural network adjusts its structure such that it will be able to follow the supervisor. The learning is repeated until the difference between network output and the supervisor is low.

Multilayer neural network controllers such as NARMA-L2 control[48] and MRC[49] have been successfully applied in the identification and control of dynamic systems. There are typically two steps involved when using neural networks for control: system identification and control design. In the system identification stage, a neural network model of the plant that is to be controlled is developed. In the control design stage, the developed neural network plant model is used to the train the controller. The system identification stage is the same for both controllers. The control design stage, however, is different for each of the architectures.

In this paper the control circuit of the series compensator shown in (Fig. 5) has been replaced by NARMA-L2 and MRC controllers and simulation was carried out using MATLAB/ Neural network blockset/control systems/NARMA-L2 and MATLAB/ Neural network blockset/control systems/MRC. The data obtained from the series compensator shown in (Fig. 5) is used to train NARMA-L2 and MRC controllers. It has been observed that the implementation of MRC is more complex than that of NARMA-L2 controller for the same output performance.

[FIGURE 5 OMITTED]

System Identification Stage: The first phase of plant identification process is to generate input/ output data to train a neural network to represent the forward dynamics of the plant. This could be achieved by either generating the training data from simulink plant model or by importing the training data from a valid data file with input and output values. The Levenberg-Marquadrat algorithm is used for training the plant model. Once the training data is acceptable a neural network could be trained to identify the function of the plant identification model described as:

y(k + d) = N[y(k),y(k – 1),…,y(k – n + 1),u(k),u(k – 1),…,u(k – n + 1)] (8)

where u(k) is the system input, y(k) is the system output and d is the system delay.

To determine the control input that causes the plant output to follow a specific reference, the controller could be identified using the expression

u(k) = [[[y.sub.r](k + d) – f[y(k),y(k – 1),…,y(k – n + 1),u(k – 1),…,u(k – m + 1)]]/[g[y(k),y(k – 1),…,y(k – n + 1),u(k – 1),.u(k – m + 1)]]] (9)

However determination of the control input based on the output at the same time is not realistic and

y(k + d) = f[y(k),y(k – 1),..(y(k – n + 1)),u(k),u(k – 1)….u(k – n + 1)] + g[y(k),…y(k – n + 1),u(k)…u(k – n + 1)].u(k + 1) (10)

And the controller is then given by the following equation

u(k + 1) = [[[y.sub.r](k + d) – f[y(k),..,y(k – n + 1),u(k),..,u(k – n + 1)]]/[g[y(k),…,y(k – n + 1),u(k),..u(k – m + 1)]]] (11)

(Fig. 6) shows the block diagram representation of the system identification stage. The plant model predicts future plant outputs. The plant model has only one hidden layer.

[FIGURE 6 OMITTED]

NARMA-L2 controller: (Fig. 7) is the block diagram representation of NARMA-L2 controller. NARMA-L2 controller requires less computation compared with MRC. The controller is simply a rearrangement of the plant model. This controller could be identified with the hence uses the model previously identified neural network plant model. The main idea of this type of control is to transform nonlinear system dynamics by canceling the nonlinearities.

[FIGURE 7 OMITTED]

Unlike the NARMA-L2 controller, model reference controller uses two neural networks: a plant model network and a controller network. To train the controller, first of all a neural network plant model has to be identified and trained as in NARMA-L2 controller, following that training data has to be generated using either a simulink reference model or by importing data from a MATLAB file. (Fig.8) is the block diagram representation of the model reference controller. Plant identification stage is the same as that of NARMA-L2 controller. The Levenberg-Marquadrat algorithm is used for training the neural network plant model. Following the plant identification stage the controller should be trained so that NN plant model output follows NN reference model output. The controller training is computationally expensive and time consuming as it requires dynamic back propagation. The BFGS (Broyden, Fletcher, Goldfarb, and Shanno) training algorithm was used to train the controller.

[FIGURE 8 OMITTED]

Model reference controller: As MRC requires a separate a controller network and dynamic back propagation algorithm is used to train the controller, the model reference controller training is more time consuming and complex than that of NARMA-L2 controller.

Design Parameters of UPQC System: The design values of the developed UPQC system are as follows:

Supply voltage – 400 V (rms, line-to-line)

DC Voltage – 750 V

DC Link Capacitor – 8.2 mF

Booster inductance – 500 [micro]H

Injection transformer – 750kVA, 500V/2,000V, Y / [DELTA]

SIMULATION RESULTS

Using MATLAB 7.0 toolbox the entire UPQC system has been modeled. The shunt compensator control circuit has been implemented using PI and FLC to regulate the capacitor voltage and HCC to generate switching signals, whereas series compensator is independently controlled using conventional and neural network controllers. The performance of the UPQC system has been analyzed using combination of conventional and ANN controllers in the shunt and series control circuits. The validity of the system for control applications such as voltage and current harmonic eliminations, reactive power compensation, voltage regulation, control of negative and zero sequence components voltage and current, elimination of voltage interruption under short circuit condition has been examined. Simulation results are detailed in the following sub-sections. Simulation results clearly illustrate the successful application of neural network controllers for the implementation of UPQC. Timing details of UPQC are tabulated in Table. 2.

Table 2: UPQC timing

Time (s) 0-0.1 0.1-0.2 0.2-0.3 0.3-0.4

DVR OFF OFF ON ON

APF OFF ON OFF ON

A. Elimination of Voltage Interruption at the Time of Short Circuit: Ideally utility must maintain rated power at rated magnitude and frequency at consumer terminals. However due to unavoidable short circuit conditions such as single line to ground, line to line, double line to ground faults there can be voltage interruption, negative and zero sequence components etc. The performance of the NARMA-L2 based UPQC has been analyzed with [R.sub.la] = 3 + j240 [ohm]; [R.sub.lb] = 20 + j 1.13 [ohm]; [R.sub.lc] = 15 [ohm] and by introducing a single line to ground fault in phase A at t = 0.05 s at the source side. Analysis of simulation results shown in (Fig. 9), (Fig. 10), and (Fig. 11) indicates that UPQC is able to maintain the terminal voltage at rated magnitude and frequency under short-circuit condition. Both DVR and APF are OFF until 0.05 s. At t = 0.05 s due to the short circuit, the source current in phase A increases to a very large value as illustrated in (Fig. 9). From 0.1 s to 0.2 s as the APF system is ON the source currents in phase B and phase C also increase. From 0.2 s to 0.4 s as the DVR is ON, the receiving end voltage is maintained at rated magnitude and frequency as illustrated in (Fig. 11) and the load currents also reach the expected values as plotted in (Fig. 10).

[FIGURE 9 OMITTED]

[FIGURE 10 OMITTED]

[FIGURE 11 OMITTED]

B. Control of Negative and Zero Sequence Components: The adverse effect of negative and zero sequence components in an unbalanced system could be eliminated by the use of a UPQC system. The performance of the system has been analyzed using MRC with [R.sub.la] = 3 + j240 [ohm]; [R.sub.lb] = 20 + j 1.13 [ohm]; [R.sub.lc] = 15 [ohm] and the resulting waveforms of source current, load current and receiving end voltage are plotted in figures 12, 13, and 14 respectively. In (Fig. 12), the source currents [i.sub.sa], [i.sub.sb], and [i.sub.sc] are balanced sinusoids indicating the successful operation of APF system from 0.1 s to 0.2 s and from 0.3 s to 0.4 s. The DVR system switched ON at 0.2 s is able to maintain the terminal voltage at rated magnitude and frequency as shown in (Fig. 14).

[FIGURE 12 OMITTED]

[FIGURE 13 OMITTED]

[FIGURE 14 OMITTED]

C. Elimination of Harmonics: The waveform of electrical power generated is purely sinusoidal and free from any distortions. Most of the electrical equipments are designed to operate under pure sinusoidal operating conditions. However the applications of nonlinear loads distort the voltage and current waveforms and these distortions may propagate all over the electrical network results into reduced equipments life, measurement errors, faulty timing signals, maloperation, and overheating etc. Harmonic control and reactive power compensation of static power converters specified in IEEE-519 standard limits the total harmonic distortions (THD) to 5 %. The developed UPQC system has been tested for harmonic elimination and reactive power compensation. Simulation results shown in (Fig. 15)-(Fig. 19) using conventional controllers with a diode rectifier load clearly indicate the effectiveness of the system to eliminate voltage and current harmonics and to improve the power factor. In (Fig. 15), the source current waveform for phase A is plotted, whereas the THD of source and load currents are plotted in (Fig. 16).

[FIGURE 15 OMITTED]

[FIGURE 16 OMITTED]

The successful operation of DVR system for the elimination of voltage harmonics is illustrated in Fig. 17 and Fig. 19. Fig. 18 indicates the secondary voltage injection using conventional controllers. THD of source current ([I.sub.sthd]), THD of load current ([I.sub.lthd]), amplitude of source current ([Ism), amplitude of load current ([I.sub.lm]), displacement power factor (DPF), THD of receiving end voltage ([V.sub.rthd]), the amplitude of the per phase receiving end voltage ([V.sub.rm]) and the phase angle of receiving end per phase voltage ([V.sub.r[phi]]) using PI controller in the shunt compensation circuit and NARMA-L2 controller and model reference controller in the series compensation circuit with different firing angles are tabulated in Table. 3-Table. 5. Table. 6 indicates the simulation results using FLC in the shunt compensation control circuit and conventional controller in the series control circuit.

[FIGURE 17 OMITTED]

[FIGURE 18 OMITTED]

[FIGURE 19 OMITTED]

Table 3: UPQC performance with thyristor rectifier load

Controller PI -NARMA-L2

[alpha] 5[degrees]Time (s) 0-0.1 0.1-0.2 0.2-0.3 0.3-0.4

[I.sub.sthd] (%) 75 0.18 1.2 0.6[I.sub.lthd] (%) 75 75 1.2 1.1[I.sub.sm] (A) 0.36 137 300 400[I.sub.lm] (A) 0.35 0.35 300 285DPF angle [degrees] -33 -10 -13.5 -17.5

[V.sub.rthd] (%) 400 300 2 1.5[V.sub.rm] (V) 0.37 0.37 300 290[V.sub.r[phi]][degrees] 20 -20 -12 -17Table 4: UPQC performance with thyristor rectifier load

Controller PI -NARMA-L2

[alpha] 20[degrees]Time (s) 0-0.1 0.1-0.2 0.2-0.3 0.3-0.4

[I.sub.sthd] (%) 75 0.18 3.3 1.9[I.sub.lthd] (%) 78 70 3.3 3.5[I.sub.sm] (A) 0.38 137 300 400[I.sub.Lm] (A) 0.38 0.38 300 285DPF angle [degrees] -33 -10 -14 -18

[V.sub.rthd] (%) 300 220 5 4.5[V.sub.rm] (V) 5 5 300 290[V.sub.r[phi]][degrees] 20 -20 -13 -17Table 5: UPQC performance with thyristor rectifier load

Controller PI – MRC

[alpha] 15[degrees]Time (s) 0-0.1 0.1-0.2 0.2-0.3 0.3-0.4

[I.sub.sthd] (%) 75 0.18 2.35 1.33[I.sub.lthd] (%) 75 75 2.3 2.4[I.sub.sm] (A) 0.75 137 300 410[I.sub.Lm] (A) 0.75 0.75 300 285DPF angle [degrees] -33 -10 -14 -18

[V.sub.rthd] (%) 300 300 3.6 3.2[V.sub.rm] (V) 4.2 4.2 300 290[V.sub.r[phi]][degrees] 10 -18 -13 -17Table 6: UPQC performance with diode rectifier load

Controller FLC- Con.

Time (s) 0-0.1 0.1-0.2 0.2-0.3 0.3-0.4

[I.sub.sthd] (%) 72 0.185 1.8 1.0[I.sub.lthd] (%) 73 73 1.8 2.2[I.sub.sm] (A) 0.37 137.1 285 400[I.sub.Lm] (A) 0.37 0.37 288 280DPF angle [degrees] -37 -0.985 -27 -27

[V.sub.rthd] (%) 73 73 4 4.2[V.sub.rm] (V) 0.7 0.7 330 330[V.sub.r[phi]][degrees] 10 -18 -13 -17CONCLUSION

An AI based UPQC system has been modeled using MATLAB toolbox. The novelty of this paper lies in the application of NNC algorithms such as MRC, and NARMA- L2 control to generate switching signals for the series compensator of the UPQC system. The performance of the system for applications such as voltage interruption, control of zero and negative sequence components, harmonic elimination and reactive power compensation has been successfully examined and analyzed. The implementation of MRC is more complex than that of NARMA-L2 controller for the same output performance.

ACKNOWLEDGMENT

The author is grateful to N. C. Sahoo, B. Venkatesh Abdulazeez S. Boujarwah, Christo George, K. S. Suresh Kumar, K. Padmakumari, K. P. Mohandas, and Ashok. S.

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Corresponding Author: Moleykutty George, Lecturer, Faculty of Engineering and Technology, Multimedia University, Melaka Campus, 75450 Melaka, Malaysia

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